1. Field of the Invention
Example embodiments of the present invention relate generally to a sense amplifier-based flip flop and method thereof, and more particularly to a sense amplifier-based flip flop and method of reducing an output delay time.
2. Description of the Related Art
Mobile devices, such as cellular phones, Personal Digital Assistants (PDAs), notebook computers, etc., may include power management systems because conventional mobile devices may include higher storage capacities as well as higher clock speeds and may be embodied using very large scale integration (VLSI). Such power management systems may seek to reduce power consumption of the mobile devices without significantly affecting performance.
The circuit structure of a conventional VLSI system may be divided into two functions. A first function may be a “logic function” to output a given signal in response to an input signal, and a second function may be a “memory function” to store an input signal in response to a clock signal or, alternatively, to output a stored signal. A circuit configured to execute a memory function may typically include one or more flip-flops.
An example of a conventional flip-flop may be a sense amplifier-based flip-flop. The sense amplifier-based flip-flop may typically include a master latch and a slave latch. A current sensing type sense amplifier circuit may be used as the master latch, and a setup time of that master latch may be relatively short. A NAND type RS latch may be used as the slave latch, in which a relatively stable operation may be maintained at higher clock speeds.
FIG. 1 is a circuit diagram illustrating a conventional sense amplifier-based flip-flop.
Referring to FIG. 1, the sense amplifier-based flip-flop may include a first latch 10, a second latch 20 and a current passing unit 30, 32. The first latch 10 may include PMOS transistors PM1, PM2, PM3 and PM4, and NMOS transistors NM1, NM2, NM3, NM4 and NM5. The second latch 20 may be a general NAND type RS latch. Hereinafter, an RS latch may be alternatively referred to as an SR latch.
Referring to FIG. 1, in the first latch 10, PMOS transistor PM1 may be connected between a power terminal VDD and an output node N1, and may operate in response to a clock signal CLK. The output node N1 and an output node N2 may be an output terminal of the first latch 10 and may further function as an input terminal of the second latch 20.
Referring to FIG. 1, PMOS transistor PM2 and NMOS transistors NM1 and NM3 may be disposed between power terminal VDD and a drain terminal N5 of an NMOS transistor NM5. The NMOS transistor NM5 may operate in response to clock signal CLK. Gate terminals of the PMOS transistor PM2 and the NMOS transistor NM1 may be connected in common to output node N2, and an input signal D may be applied to a gate terminal of the NMOS transistor NM3. The PMOS transistor PM3 may be disposed between power terminal VDD and output node N2, and may operate in response to clock signal CLK. PMOS transistor PM4 and NMOS transistors NM2 and NM4 may be connected between power terminal VDD and a drain terminal N5 of NMOS transistor NM5. Gate terminals of the PMOS transistor PM4 and the NMOS transistor NM2 may be connected in common to output node N1, and input signal /D may be applied to a gate terminal of the NMOS transistor NM4.
Referring to FIG. 1, the current passing unit 30, 32 may include a plurality of NMOS transistors NM11, NM12, NM13, NM14, NM15, NM16. A first current passing unit 30 may include a plurality of NMOS transistors NM11, NM12 and NM13, and a second current passing unit 32 may include a plurality of NMOS transistors NM14, NM15 and NM16. The first current passing unit 30 may provide a path in which current of a node N3 may flow to a ground terminal if the clock signal is set to a first logic level (e.g., a higher logic level or logic “1”), and may alternatively cut off the current path if the clock signal is set to a second logic level (e.g., a lower logic level or logic “0”). Likewise, the second current passing unit 32 may provide a path in which current of a node N4 may flow to a ground terminal if the clock signal is set to the first logic level, and may cut off the current path if the clock signal is set to the second logic level.
Referring to FIG. 1, the conventional sense amplifier-based flip-flop including the first latch 10 and the second latch 20 connected to the first latch 10 may be referred to as a sense amplifier D flip-flop because the sense amplifier-based flip-flop may operate as a D flip-flop that may have an applied input signal D, /D and may output an output signal Q, /Q delayed in response to clock signal CLK.
Conventional operation of the sense amplifier-based flip-flop circuit of FIG. 1 will now be described.
In conventional operation of the sense amplifier-based flip-flop circuit of FIG. 1, if clock signal CLK transitions to the second logic level (e.g., a lower logic level or logic “0”), output node N1, N2 may be set to the first logic level (e.g., a higher logic level or logic “1”) irrespective of input signal D. In other words, if the clock signal CLK is set to the second logic level, the output node N1 may be set to the first logic level by a turn-on operation of PMOS transistor PM1, and the output node N2 may be set to the first logic level by a turn-on of PMOS transistor PM3. Input signals R and S may be set to the first logic level, and output signals Q and /Q of the second latch 20 may maintain their respective values (e.g., in a precharge state of the sense amplifier-based flip-flop of FIG. 1).
In conventional operation of the sense amplifier-based flip-flop circuit of FIG. 1, if the clock signal CLK transitions to the first logic level (e.g., a higher logic level or logic “1”), a voltage level at output nodes N1 and N2 may be affected by a state of input signal D, /D. In an example, the input signal D, /D may refer to a signal including opposite logic levels (e.g., D set to the first logic level and /D set to the second logic level, or vice versa). Alternatively, the input signal D, /D may be set to the same logic level. For example, if the clock signal CLK is set to the first logic level (e.g., a higher logic level or logic “1”) and the input signal D has a voltage or logic level higher than the input signal /D, NMOS transistor NM3 may be turned on to a greater degree than an NMOS transistor NM4. A main current path herein may be current passing unit 30, 32. However, if the NMOS transistor NM3 is turned on to a higher degree than the NMOS transistor NM4, current flowing from node N3 to ground terminal through node N5 may be greater than current flowing from node N4 to the ground terminal through the node N5. Thus, a voltage level of the node N3 may be lower than a voltage level of the node N4. Further a voltage level difference between output node N1 and output node N2 may be sufficient to detect a logic level difference (e.g., between the first and second logic levels). Signals of the output nodes N1 and N2 may thereby be provided as input signals R and S of the second latch 20.
In conventional operation of the sense amplifier-based flip-flop circuit of FIG. 1, if the clock signal CLK transitions to the first logic level (e.g., a higher logic level or logic “1”) and the input signal D has a voltage level lower than that of the input signal /D, an opposite result as above-described may occur. In other words, the output node N1 may be set to a higher voltage level and the output node N2 may be set to a lower voltage level. In an example, if the current passing unit 30, 32 is not included within the sense amplifier-based flip-flop of FIG. 1, a duration for current to propagate from the nodes N3 and the node N4 to the ground terminal may be lengthened if the clock signal CLK is set to the first logic level (e.g., a higher logic level or logic “1”). Accordingly, the current passing unit 30, 32 may reduce the duration of current propagation, thereby reducing an output delay time, which may be called a CLK to Q delay, from a transition of clock signal CLK to a final output Q, /Q. Thereby, the current passing unit 30, 32 may improve a performance of the sense amplifier-based flip-flop.
For example, output nodes N1 and N2 may be precharged if the clock signal CLK is set to the second logic level (e.g., a lower logic level or logic “0”). Alternatively, if the clock signal CLK is set to the first logic level (e.g., a higher logic level or logic “1”), voltage levels of the output nodes N1 and N2 may be based upon a voltage level difference between input signal D and input signal /D. A time period provided when the clock signal CLK is set to the first logic level (e.g., a higher logic level or logic “1”) may be referred to as an “evaluation period”. The first latch 10 may have an evaluation state within the evaluation period. Signals output from the output nodes N1 and N2 during the evaluation period may be referred to as evaluation signals.
FIG. 2 illustrates signal levels during an operation of the conventional sense amplifier-based flip-flop of FIG. 1. In particularly, in FIG. 2, signal levels of clock signal CLK, input signal D, /D and output node N1, N2, N3, N4 are illustrated.
Referring to FIG. 2, if the clock signal CLK is set to the second logic level (e.g., a lower logic level or logic “0”), each of the output nodes N1, N2, N3 and N4 may be maintained at the first logic level (e.g., a higher logic level or logic “1”). If the clock signal CLK transitions to the first logic level, the level of the output nodes N1, N2, N3, N4 may be changed in response to the transition.
Referring to FIG. 2, as a review of the respective voltages at nodes N1, N2 and nodes N3, N4 will reveal, the wave of node N1, N2 may experience a given delay period as compared to the nodes N3, N4.
Referring to FIG. 2, a period from the transition of the clock signal CLK to an applied time of output signal Q, Q′ of the second latch 20 may be illustrated, and delay time t1 may be indicative of a period from the transition time of the clock signal CLK to an output time of output node N1, N2 of the first latch 10. The latch operation of the second latch 20, while not specifically illustrated, may be the same as described above. The delay time t1 may be an output delay time from a transition of the clock signal CLK to a final output Q, Q′.
As described above, the conventional sense amplifier-based flip-flop may reduce an output delay time from a transition time of a clock signal to a final output signal via a current passing unit. However, the use of the current passing unit may decrease an input sensitivity of the conventional sense amplifier-based flip-flop. Thus, if a voltage level difference of input signals is relatively small, the sense amplifier-based flip-flop may not detect the voltage difference, thereby increasing the likelihood of data loss and/or operation error.